The present invention relates to a multi-gate, fin-based field effect transistor (FinFET), and more specifically, to hybrid shallow trench isolation (STI) with both shallow and deep STI.
Multi-gate FinFETs require both shallow and deep STIs to prevent leakage current between adjacent devices. Typically, FinFET devices are fabricated by shallow STI formation followed by an active silicon cut process to etch out the active silicon region and form deep STI. Overlay misalignment during this process may cause the end fins to not be completely covered by the polysilicon conductor. As a result, the end fins submerged in the STI without polysilicon deposition may lead to poor short channel control and may potentially lead to leaks.